The crystal or quartz oscillator is one of the most used circuits in integrated LSI, VLSI and ULSI devices, primarily for generating a highly stable base clock frequency.
Commonly, high frequency crystal oscillators, for example operating above 20 MHz, employ a series-resonant quartz crystal, coupled through a lead of the integrated device, to an integrated oscillator circuit which may have one of many known circuit configurations. For example the oscillator circuit may be realized as a closed loop of inverters connected in series or according to one of other commonly used configurations such as the so called Pierce, Colpitts, Clapp configuration and others yet. Notwithstanding the excellent stability of the frequency of oscillation intrinsic to any quartz oscillator, numerous other aspects of the particular oscillator circuit assume a great importance in designing an integrated device comprising a crystal oscillator. An oscillator circuit based on a closed chain of inverters may have the tendency of oscillating at higher intrinsic frequencies of the quartz crystal, but above all it requires a relatively large area of integration, which is hardly compatible in high density integrated systems (VLSI, ULSI). Pierce, Colpitts or Clapp configured oscillators, as well as the inverter-ring ring oscillator, normally require two pins and several external components. Also this aspect is hardly compatible with the scarcity of available pins in packages containing monolithically integrated complex systems integrated on the same chip and with the general requirement of limiting to the minimum the number of external components.
More recently crystal oscillators have been developed and employed in integrated circuits in Pierce or Colpitts configuration, that require only one pin for connection to the external quartz crystal. The article entitled: "A One-Pin Crystal Oscillator for VLSI Circuits" by Joseph T. Santos and Robert G. Meyer, IEEE Journal of Solid-State Circuits, Vol. SC-19, Nr. 2, Apr. 1984, discloses a one-pin crystal oscillator in a Pierce configuration. The article entitled: "Design Consideration for High-Frequency Crystal Oscillator" by Mehmet Soyuer, IEEE Journal of Solid-State Circuits, Vol. 26. Nr. 6, Jun. 1991, describes the characteristics of different types of series resonant crystal oscillators in various configurations. More generally the volume: "Crystal Oscillator Design and Temperature Compensation" by Marvin E. Frerking, Van Nostrand Reinhold Co., contains a broad review of the known circuits.
Typically an oscillator circuit employs as a gain stage an emitter or source follower and an oscillating tank circuit for selecting a particular resonance frequency of the crystal. Generally high frequency quartz oscillators function with the crystal in a series resonant mode in order to overcome the influence of the parasitic reactances of the circuit. In general, for oscillators working at a frequency comprised between 50 and 125 MHz, the fifth order, natural frequency of resonance of the crystal is used while for higher frequencies a resonance frequency of a higher order, for example the seventh may be used.
In case of integrated oscillator circuits, for the above noted reasons, compensation of the intrinsic impedance of the crystal at its series resonance frequency by using an inductance may be too burdensome and therefore other systems of compensation that do not require the use of external components must be adopted.
However, also the means used for temperature compensating the oscillator must be compatible with the requirements imposed by the use of a single pin and by the requisite of monolithically integrating of the entire circuit.
A Colpitts configured oscillator, fabricated with a bipolar technology, that is employing as a gain stage an emitter follower stage using a bipolar junction transistor (BJT) in a grounded collector configuration, is burdensome in terms of occupied silicon area.
On the other hand, realizing the oscillator circuit with a MOS technology, that is employing a source follower gain stage using a field effect transistor (MOS) in a grounded drain configuration, though reducing the silicon area of integration, may introduce problems of criticality at start-up by delaying the start-up process.